The present invention relates to the field of semiconductor devices; more specifically, it relates to lateral diodes and lateral bipolar transistors and the method of fabricating said diodes and transistors.
In both silicon-on-insulator (SOI), bipolar/complementary metal-oxide-silicon (BICMOS) and SiGe BICMOS technologies there is a need for diodes and non-SiGe bipolar transistors.
One type of diode available to SOI/CMOS technology is a gated diode. Gated diodes use a dummy gate over the PN junction. The dielectric spacers formed on the sidewalls of the dummy gate prevent the silicide contact process from shorting out the junction. However, gated diodes, especially as the gate oxide becomes thin, can suffer from the problem of the leakage current through the dummy gate being greater than the leakage current through the diode, resulting in excessive power consumption.
In BICMOS technology there is a need for transistors capable of running at voltages higher than the gate dielectric breakdown voltages of the CMOS transistors. One such need is found in pre-amplifier circuits. One type of bipolar transistor available for BICMOS and SiGe BICMOS technology is a lateral bipolar transistor wherein the base width of the transistor is defined by the CMOS gate process, which also prevents the silicide contact process from shorting out the emitter, base and collector. The emitter and collector are defined by the CMOS source/drain (S/D) dopant processes. However, the resultant bipolar transistor exhibits both FET and bipolar characteristics and is difficult to model.
A diode and lateral bipolar transistor, fabricated without the use of CMOS gate technology to prevent the junctions of the diode and the emitter, base and collector of the transistor from shorting would result in devices with lower leakages and purer diode and bipolar transistor characteristics and allow voltages to be applied to the diode and lateral bipolar transistor greater than the CMOS device gate dielectric breakdown voltage.
A first aspect of the present invention is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion, forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region
A second aspect of the present invention is a method of fabricating a lateral diode, comprising: providing a silicon substrate; forming an N-region and a P-region in the substrate, the P-region abutting the N-region and thereby forming a PN junction; and forming a protective island on a top surface of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.
A third aspect of the present invention is a method of fabricating a lateral bipolar transistor, comprising: providing a silicon substrate; forming an emitter region, a base region and a collector region in the silicon substrate, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; forming a protective island on the top surface of the silicon substrate, the protective island extending the length of the first PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the second PN junction and overlapping a portion of the collector region and a portion of the base region.
A fourth aspect of the present invention is a method of fabricating a lateral diode, comprising: providing a silicon on insulator substrate comprising a silicon layer over an insulator; forming an N-region and a P-region in the silicon layer, the P-region abutting the N-region and thereby forming a PN junction; and forming a protective island on a top surface of the silicon layer of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.
A fifth aspect of the present invention is a method of fabricating a lateral bipolar transistor, comprising: providing a silicon on insulator substrate comprising a silicon layer over an insulator; forming an emitter region, a base region and a collector region in the silicon layer, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; forming a protective island on the top surface of the silicon layer of the substrate, the protective island extending the length of the second PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the third PN junction and overlapping a portion of the collector region and a portion of the base region.
A sixth aspect of the present invention is a lateral semiconductor device, comprising: a substrate, having at least an upper silicon portion; at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.
A seventh aspect of the present invention is a lateral diode, comprising: a silicon substrate; an N-region and a P-region in the substrate, the P-region abutting the N-region and thereby forming a PN junction; and a protective island on a top surface of the silicon substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.
An eighth aspect of the present invention is a lateral bipolar transistor, comprising: a silicon substrate; an emitter region, a base region and a collector region in the silicon substrate, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; a protective island on the top surface of the silicon substrate, the protective island extending the length of the first PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the second PN junction and overlapping a portion of the collector region and a portion of the base region.
A ninth aspect of the present invention is a lateral diode, comprising: a silicon on insulator substrate comprising a silicon layer over an insulator; an N-region and a P-region in the silicon layer, the P-region abutting the N-region and thereby forming a PN junction; and a protective island on a top surface of the silicon layer of the substrate, the protective island extending the length of the PN junction and overlapping a portion of the N-region and a portion of the P-region.
A tenth aspect of the present invention is a lateral bipolar transistor, comprising: a silicon on insulator substrate comprising a silicon layer over an insulator; an emitter region, a base region and a collector region in the silicon layer, the emitter region abutting the base region and thereby forming a first PN junction and the collector region abutting the base region and thereby forming a second PN junction; a protective island on the top surface of the silicon layer of the substrate, the protective island extending the length of the second PN junction and overlapping a portion of the emitter region and a portion of the base region; and the protective island extending the length of the third PN junction and overlapping a portion of the collector region and a portion of the base region.